This invention relates to a semiconductor circuit, especially a technology on a circuit on which the ECL, MIS, and BiMIS circuits are in mixture.
Recently to effect a memory with both high speed and high integration, an ECL circuit with high speed controlling the logical amplitude and the semiconductors mixed with an MIS circuit and a BiMIS circuit with low electric power consumption although the logical amplitude extends to the power voltage, are much proposed. However the MIS or BiMIS circuit can not be directly driven by an output signal of the ECL circuit.
Accordingly a level converter circuit has been always required for the semiconductor circuit mixed with an ECL circuit and an MIS or BiMIS circuit.
FIG. 4(a) conventional configuration diagram of a semiconductor circuit mixed with an ECL circuit having an ECL interface, and an MIS or BiMIS circuit. FIG. 4(a) shows an embodiment in which the input buffer 11 is composed of an ECL circuit and the level converter circuit 12 and the driver 13 are composed of MIS or BiMIS circuits.
FIG. 4(b) is a circuit diagram showing an embodiment of the definite circuits of the input buffer 11, the level converter circuit 12, and the driver 13 in FIG. 4(a). In FIG. 4(b), the driver 13 is composed of a BiMIS circuit.
In both FIGS. 4(a) and 4(b), the power voltages of the points connected with the ECL circuit and the MIS or BiMIS circuit are all V.sub.CC (high electric potential) and V.sub.EE (low electric potential), and the power voltages applied to the ECL circuit and the MIS or BiMIS circuit are all same as V.sub.CC -V.sub.EE. Thus if making the power voltages applied to the ECL circuit and the MIS or BiMIS circuit consistent, the level converter circuit 12 is always required between the ECL circuit and the MIS or BiMIS circuit. Because the signal amplitude voltage of the ECL circuit comes lower than that of the MIS or BiMIS circuit.
Moreover, FIG. 5(a) shows a conventional configuration diagram of an MIS or BiMIS circuit having a TTL interface. FIG. 5(a) shows an example in which the input buffer 14 and the driver 13 are composed of an MIS or BiMIS circuit.
FIG. 5(b) is a circuit diagram showing an example of the definite circuit of the input buffer 14 and the driver 13 in FIG. 5(a). In FIG. 5(b), the input buffer 14 and the driver 13 are composed of BiMIS circuits.
In both FIGS. 5(a) and 5(b), the power voltages of the points connected with the MIS circuit or BiMIS circuit are all V.sub.DD (high electric potential) and V.sub.SS (low electric potential).
Accordingly a conventional construction mixed with an ECL circuit having an ECL interface, and an MIS or BiMIS circuit contains a level converter circuit.
Hereupon, to hold the TTL interface and the ECL interface in common, the level converter circuit becomes an element preventing speeding up and reducing the size.